1. Field of the Invention
The present invention relates generally to semiconductor memory devices and methods of manufacturing the same and particularly to semiconductor memory devices provided with a memory region and a logic circuit region and methods of manufacturing the same.
2. Description of the Background Art
In recent years, design technology and process technology have advanced and thus made it possible to mount conventionally separately manufactured, multiple integrated circuits on a single chip to fabricate a highly integrated circuit. Together with the high integration of integrated circuits is also pursued a rapid operation contributed to by mounting on a single chip. Semiconductor memory devices represented by dynamic random-access memory (DRAM;) have also been fabricated on the same chip as a high-level integrated logic circuit including microprocessing units (MPU). To fabricate such an integrated circuit, a plurality of metal oxide silicon (MOS) field effect transistors different in structure need to be incorporated in a single chip. A semiconductor memory device including memory cells and a logic circuit formed on a single substrate is disclosed for example in Japanese Patent Laying-Open No. 2001-291779.
FIG. 14 is a cross section of a conventional semiconductor memory device, as described in Japanese Patent Laying-Open No. 2001-291779. As shown in the figure, the conventional semiconductor memory device includes a semiconductor substrate 401, and a memory cell region 491, a logic circuit region 492 and a peripheral region 493 formed on semiconductor substrate 401.
Semiconductor substrate 401 includes a p or n impurity of approximately 1xc3x971015 cm3. In a separate region is formed an isolation and insulation film 402 formed of silicon oxide film. Isolation and insulation film 402 separates a surface of semiconductor substrate 401 and impurity is introduced into the surface to provide an n well 437, p wells 441, 442, 443 and 444, and n bottom wells 321 and 431.
In memory cell region 491 p well 443 is deeper than n well 437 to allow a DRAM formed in p well 443 to have enhanced memory retention characteristics. Furthermore, p well 443 for holding memory is surrounded by n well 437 and n bottom well 431. P well 443 can thus have a potential set independently of semiconductor substrate 401 to reduce soft error. N well 437 is provided with a p MOS transistor (not shown) accommodating a different application and p wells 441 and 444 are provided with n MOS transistors (not shown), respectively, accommodating their respective applications.
The conventional semiconductor memory device as described above, however, is disadvantageous, as described hereinafter.
Bottom well 431 is initially formed on semiconductor substrate 401 having a low impurity concentration and in contact therewith p well 443 is formed. Although p well 443 is surrounded by n well 437 and bottom well 431, soft error can be introduced and thus impair the reliability of the semiconductor device.
Furthermore, logic circuit region 492 is provided with a plurality of field effect transistors which mutually configure a complementary MOS transistor (CMOS). In the FIG. 14 conventional structure at the CMOS latch-up is caused and thus impairs the reliability of the semiconductor memory device.
The present invention has been made to overcome the disadvantages described above.
One object of the present invention is to prevent soft error to provide a highly reliable semiconductor memory device.
Another object of the present invention is to prevent latch-up to provide a highly reliable semiconductor memory device.
In accordance with the present invention a semiconductor device includes: a semiconductor substrate containing an impurity of a first conductivity type having a first concentration; a semiconductor layer formed on the second substrate, having a main surface, and containing an impurity of the first conductivity type having a second concentration lower than the first concentration; a memory region provided on the semiconductor layer; and a logic circuit region provided on the semiconductor layer at a location different from the memory region. The memory region includes a first well region of the first conductivity type formed at the semiconductor layer and having a first bottom plane at a first depth as measured from the main surface, a second well region of a second conductivity type formed at the semiconductor layer to surround the first well region and having a second bottom plane at a second depth less deep than the first depth, as measured from the main surface, and a first bottom well region of the second conductivity type provided at the semiconductor layer in contact with the first and second bottom planes. The logic circuit region includes a complementary field effect semiconductor element formed on a main surface of the semiconductor layer.
In the semiconductor memory device of the present invention configured as described above a semiconductor layer containing an impurity of a first conductivity type having a relatively low concentration is formed on a semiconductor substrate containing an impurity of the first conductivity type having a relatively high concentration. Thus the substrate of the high concentration underlies the semiconductor layer of the low concentration and on the semiconductor layer are provided a memory region and a logic circuit region. Thus the memory region can be free of soft error. Furthermore, the logic circuit region, including a complementary field effect semiconductor element, can prevent the semiconductor element from latching up. A highly reliable semiconductor memory device can thus be provided.
Furthermore, a first well region having a first bottom plane positioned to be relatively deeper, as measured from a main surface, and a second well region having a second bottom plane positioned to be relatively less deep, as measured from the main surface, can be included and providing the first well region with a memory element can thus enhance the memory element""s memory retention characteristics. Furthermore, the first well region of the first conductivity type can be surrounded by the second well region of the second conductivity type and a bottom well region of the second conductivity type and as a result the first well region can have a potential set independently to provide further enhanced resistance to soft error.
Preferably, the memory region includes a memory element formed at the first well region. The memory element includes dynamic random access memory. The memory element includes a capacitor. The logic circuit region includes a third well region of the first conductivity type provided in the semiconductor region and a fourth well region of the second conductivity type. The logic circuit region includes a field effect transistor formed in the third well region and having the second conductivity type and a field effect transistor formed in the fourth well region and having the first conductivity type. The fourth well region surrounds the third well region and the logic circuit region includes a second bottom well region provided in contact with the third and fourth well regions at their respective bottom planes and having the second conductivity type.
The present invention provides a method of manufacturing a semiconductor memory device including the steps of: epitaxially growing on a semiconductor substrate containing an impurity of a first conductivity type having a first concentration a semiconductor layer having a main surface and containing an impurity of the first conductivity type having a second concentration lower than the first concentration; forming a memory region on the semiconductor layer; and forming a logic circuit region on the semiconductor layer at a location different from the memory region. The step of forming the memory region including the step of forming a first well region of the first conductivity type formed at the semiconductor layer and having a first bottom plane at a first depth as measured from the main surface, a second well region of a second conductivity type formed at the semiconductor layer to surround the first well region and having a second bottom plane at a second depth less deep than the first depth, as measured from the main surface, and a first bottom well region of the second conductivity type provided at the semiconductor layer in contact with the first and second bottom planes. The step of forming the logic circuit region includes the step of forming a complementary field effect semiconductor element on a main surface of the semiconductor layer.
In the present method a semiconductor layer can be formed through epitaxial growth and its thickness, impurity concentration and crystal orientation can thus be controlled precisely. As a result, a highly reliable semiconductor memory device can be provided.